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FAN6982 -- CCM Power Factor Correction Controller
February 2010
FAN6982 CCM Power Factor Correction Controller
Features
Continuous Conduction Mode Innovative Switching-Charge Multiplier-Divider Average-Current-Mode for Input-Current Shaping TriFault DetectTM Prevent Abnormal Operation for Feedback Loop Power-On Sequence Control Soft-Start Capability Brownout Protection Cycle-by-Cycle Peak Current Limiting. Improves Light-Load Efficiency Fulfills Class-D Requirements of IEC 1000-3-2 Programmable Frequency: 50kHz to 130kHz Wide Range Universal AC Input Voltage Maximum Duty Cycle 97% VDD Under-Voltage Lockout (UVLO)
Description
The FAN6982 is a 14-pin, Continuous Conduction Mode (CCM) PFC controller IC intended for Power Factor Correction (PFC) pre-regulators. The FAN6982 includes circuits for the implementation of leading edge, average current, "boost"-type power factor correction, and results in a power supply that fully complies with the IEC1000-3-2 specification. A TriFault DetectTM function helps reduce external components and provides full protection for feedback loops such as open, short, and over voltage. An overvoltage comparator shuts down the PFC stage in the event of a sudden load decrease. The RDY signal can be used for power-on sequence control. The EN function can choose to enable or disable the range function. FAN6982 also includes PFC soft-start, peak current limiting, and input voltage brownout protection.
Applications
Desktop PC Power Supply Internet Server Power Supply LCD TV/Monitor Power Supply DC Motor Power Supply
Ordering Information
Part Number
FAN6982MY
Operating Temperature Range
-40C to +105C
Eco Status
Green
Package
14-Pin Small Outline Package (SOP)
Packing Method
Tape & Reel
For Fairchild's definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1
www.fairchildsemi.com
FAN6982 -- CCM Power Factor Correction Controller
Application Diagram
Figure 1. Typical Application
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1
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FAN6982 -- CCM Power Factor Correction Controller
Block Diagram
14 1 11
VEA Low-Power Detect Comparator
IEA
0.5V PFC UVP
VDD
7.5V REFERENCE
S
SET
VREF
12
2.75V/2.5V VDD 28V/27V -1.15V ISENSE 1.05V/1.9V VRMS
PFC OVP
Q
FBPFC 2.5V
13
0.3V GmV
RM
GmI
VDD OVP PFC ILIMIT VIN UVP
R
CLR
Q
6
EN
OPFC
10
Range
VRMS
4 2
k 2 x
S
SET
Q
VEA
PGND
9
IM O IAC
R
CL R
Q
Gain Modulator
RM
2.8V VDD
3
ISENSE
UVLO
RDY
5
7
RT/CT
OSCILLATOR
FBPFC 2.4V/1.15V
SGND
8
Figure 2. Functional Block Diagram
Marking Information F - Fairchild Logo Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die-Run Code T - Package Type (M: SOP) P - Y: Green Package M - Manufacture Flow Code
Figure 3. Top Mark
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1
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FAN6982 -- CCM Power Factor Correction Controller
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Name
IEA IAC ISENSE VRMS RDY EN RT/CT SGND PGND OPFC VDD VREF FBPFC VEA
Description
Output of Current Amplifier. This is the output of the PFC current amplifier. The signal from this pin is compared with sawtooth and determines the pulsewidth for PFC gate drive. Input AC Current. For normal operation, this input is used to provide current reference for the multiplier. The suggested maximum IAC is 100A. Current Sense. The non-inverting input of the PFC current amplifier and the output of multiplier and PFC ILIMIT comparator. Line-Voltage Detection. The pin is used for PFC multiplier. Ready Signal. This pin controls the power-on sequence. Once the FAN6982 is turned on and the FBPFC voltage exceeds in 2.4V, the RDY pin pulls LOW impedance. If the FBPFC voltage is lower than 1.15V, the RDY pin pulls HIGH impedance. Enable Range Function. The range function is enabled when EN is connected to VREF. The range function is disabled when EN is connected to GND. Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT. Signal Ground. Power Ground. Gate Drive. The totem-pole output drive for PFC MOSFET. This pin is internally clamped under 15V to protect the MOSFET. Power Supply. The threshold voltages for startup and turn-off are 11V and 9.3V, respectively. The operating current is lower than 10mA. Reference Voltage. Buffered output for the internal 7.5V reference. Voltage Feedback Input. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. Output of Voltage Amplifier. The error-amplifier output for PFC voltage feedback loop. A compensation network is connected between this pin and ground.
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1
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FAN6982 -- CCM Power Factor Correction Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD VH VL VIEA VN IAC IREF IPFC-OUT PD R j-a R j-c TJ TSTG TL ESD DC Supply Voltage OPFC, RDY, EN, VREF
Parameter
Min.
-0.3 -0.3 0 -5.0
Max.
30 30.0 7.0 VVREF+0.3 0.7 1 5 0.5 800 104.10 40.61
Unit
V V V V V mA mA A mW C/W C/W C C C kV
IAC, VRMS, RT/CT, FBPFC, VEA IEA ISENSE Input AC Current VREF Output Current Peak PFC OUT Current, Source or Sink Power Dissipation, TA < 50C Thermal Resistance (Junction-to-Air) Thermal Resistance (Junction-to-Case) Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering) Electrostatic Discharge Capability Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101
-40 -55
+125 +150 +260 4.5 1.0
Notes: 1. All voltage values, except differential voltage, are given with respect to the GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
Min.
-40
Max.
+105
Unit
C
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1
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FAN6982 -- CCM Power Factor Correction Controller
Electrical Characteristics
Unless otherwise noted; VDD=15V, TA= 25C, TA=TJ, RT=27k, and CT=1000pF.
Symbol
VDD Section VDD-OP IDD ST IDD-OP VTH-ON VTH VDD-OVP VDD-OVP Oscillator fOSC
(3) fDV
Parameter
Continuously Operating Voltage Startup Current Operating Current Turn-on Threshold Voltage Hysteresis VDD OVP VDD OVP Hysteresis PFC Frequency Voltage Stability Temperature Stability Total Variation Ramp Voltage Discharge Current Frequency Range PFC Dead Time Reference Voltage Load Regulation of Reference Voltage
Conditions
Min.
Typ.
Max.
Units
22 VDD=VTH-ON-0.1V; OPFC Open VDD=13V; OPFC Open 2.0 10 1.35 27 28 1 RT=27k, CT=1000pF 11V VDD 22V -40C ~ +105C Line, Temperature Valley-to-Peak VRAMP=0V, VRT/CT=2.5V RT=27k, CT=1000pF IREF=0mA, CREF=0.1F CREF=0.1F, IREF=0mA to 3.5mA VVDD=14V, Rise/Fall Time > 20s 6.5 50 400 7.4 600 7.5 30 58 2.8 15.0 75 800 7.6 50 25 0.4 7.35 5 5 1.00 1.85 750 340 1.05 1.90 850 410 1.10 1.95 950 480 0.5 7.65 25 60 64 67 2 2 70 30 2.3 11 80 3.0 12 1.90 29
V A mA V V V V kHz % % kHz V mA kHz ns V mV mV % V mV mA V V mV ms
fDT
(3)
fTV fRV IOSC-DIS fRANGE tPFC-DEAD VREF VVREF VVREF1 VVREF2 VVREF-DT VVREF-TV VVREF-LS IREF-MAX Brownout VRMS-UVL VRMS-UVH VRMS-UVP tUVP RDY Section VFBPFC-RD VFBPFC-RD IRDY-LEK VRDY-L
Line Regulation of Reference CREF=0.1F, VVDD=11V to 22V Voltage Temperature Stability Total Variation
(3) (3) (3)
-40C ~ +105C Line, Load, Temperature TJ=125C, 0 ~ 1000HRs VVREF > 7.35V When VRMS=1.05V at 75 VRMS When VRMS=1.9V at 85 * 1.414
Long-Term Stability Maximum Current
VRMS Threshold Low VRMS Threshold High Hysteresis Under-Voltage Protection Debounce Time FBPFC Voltage Level to Pull Low Impedance with RDY Pin Hysteresis Leakage Current of RDY High Impedance RDY Low Voltage
2.3 1.15 VFBPFC<2.4V ISINK=2mA
2.4 1.25
2.5 1.35 500 0.5
V V nA V
Continued on the following page...
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1 www.fairchildsemi.com 6
FAN6982 -- CCM Power Factor Correction Controller
Electrical Characteristics (Continued)
Unless otherwise noted; VDD=15V, TA= 25C, TA=TJ, RT=27k, and CT=1000pF.
Symbol
VREF AV GmV IFBPFC-L IFBPFC-H IBS VVEA-H VVEA-L VISENSE AI GmI VOFFSET VIEA-H VIEA-L IL IH VFBPFC-OVP
Parameter
Reference Voltage Open-Loop Gain
(3)
Conditions
Min.
2.45
Typ.
2.50 42 70 50 -50
Max.
2.55 90 -40 1
Units
V dB mho A A A V V V dB mho mV V V A A V mV V V V V
Voltage Error Amplifier At TA=25C VNONINV=VINV, VVEA=3.75V at TA=25C VFBPFC=2V, VVEA=1.5V VFBPFC=3V, VVEA=6V -1 5.8 6.0 0.1 -1.5 At TA=25C VNONINV=VINV, VIEA=3.75V VVEA=0V, IAC Open 40 75 -10 6.8 VISENSE= -0.6V, VIEA=1.5V VISENSE= +0.6V, VIEA=4.0V 2.70 200 0.2 VFBPFC < 2.4V VEN=VVREF VEN=GND When VVRMS=1.95V at 132VRMS When VVRMS=2.45V at 150 VRMS When VVEA=1.95V at 30% Loading When VVEA=2.45V at 40% Loading 1.90 2.40 1.90 2.40 18 2.2 7.4 35 7.4 0.1 50 -50 2.75 250 0.3 2.8 7.5 0 1.95 2.45 1.95 2.45 20 20.00 2.50 2.00 2.50 22 -35 2.80 300 0.4 3.3 7.6 50 88 100 10 8.0 0.4 0.4 0.7 35 50 40
Transconductance Maximum Source Current Maximum Sink Current Input Bias Current Output High Voltage on VVEA Output Low Voltage on VVEA Input Voltage Range Open-Loop Gain
(3)
Current Error Amplifier
Transconductance Input Offset Voltage Output High Voltage Output Low Voltage Source Current Sink Current Over Voltage Protection
PFC OVP Comparator VFBPFC-OVP PFC OVP Hysteresis Low-Power Detect Comparator VVEA-OFF VVEA_CLAMP EN Section VEN-H VEN-L Range VVRMS-L VVRMS-H VVEA-L VVEA-H ITC RMS AC Voltage Low RMS AC Voltage High VEA Low VEA High Source Current from FBPFC V V V V A High Voltage Level of VEN Low Voltage Level of VEN VEA Voltage Off OPFC PFC Soft-Start PFC Soft-Start
Continued on the following page...
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1
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FAN6982 -- CCM Power Factor Correction Controller
Electrical Characteristics (Continued)
Unless otherwise noted; VDD=15V, TA= 25C, TA=TJ, RT=27k, and CT=1000pF.
Symbol
Gain Modulator IAC
Parameter
Input for AC Current
Conditions
Multiplier Linear Range IIAC=17.67A, VVRMS=1.080V VFBPFC=2.25V, at TA=25C IIAC=20A, VVRMS=1.224V VFBPFC=2.25V, at TA=25C
Min.
0 7.500 6.367 3.801 0.950 0.660
Typ.
Max.
100
Units
A
9.000 7.004 4.182 1.045 0.726 2
10.500 7.704 4.600 1.149 0.798 kHz 0.885 V
GAIN
Gain Modulator
(3)(4)
IIAC=25.69A, VVRMS=1.585V VFBPFC=2.25V, at TA=25C IIAC=51.62A, VVRMS=3.169V VFBPFC=2.25V, at TA=25C IIAC=62.23A, VVRMS=3.803V VFBPFC=2.25V, at TA=25C
BW VO(GM)
Bandwidth Output Voltage=5.7k x (ISENSE-IOFFSET) Peak Current Limit Threshold Voltage Cycle-by-Cycle Limit PFC ILIMIT-Gain Modulator Output Gate Output Clamping Voltage Gate Low Voltage Gate High Voltage Gate Rising Time Gate Falling Time Maximum Duty Cycle Minimum Duty Cycle
IIAC=40A IAC=20A, VRMS=1.224V VFBPFC=2.25V, at TA=25C 0.710
0.798
PFC ILIMIT Comparator VPFC-ILIMIT Vpk -1.25 IIAC=17.67A, VVRMS=1.08V VFBPFC=2.25V, at TA=25C 200 -1.15 -1.05 V mV
PFC Output Driver VGATE-CLAMP VGATE-L VGATE-H tR tF DPFC-MAX DPFC-MIN VDD=22V VDD=15V; IO=100mA VDD=13V; IO=100mA VDD=15V; CL=4.7nF; O/P= 2V to 9V VDD=15V; CL=4.7nF; O/P= 9V to 2V VIEA<1.2V VIEA>4.5V VFBPFC=VFBPFC-OVP to FBPFC OPEN, 470pF from FBPFC to GND 0.4 8 40 40 94 70 60 97 0 120 110 13 15 17 1.5 V V V ns ns % %
Tri-Fault Detect tFBPFC_OPEN VPFC-UVP Time to FBPFC Open PFC Feedback UnderVoltage Protection 2 0.5 4 0.6 ms V
Notes: 3. This parameter, although guaranteed by design, is not 100% production tested. 4. This gain is the maximum gain of modulation with a given VRMS voltage when VEA is saturated to high.
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1
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FAN6982 -- CCM Power Factor Correction Controller
Typical Performance Characteristics
3.0 2.9 2.8 2.7 29.0 28.8 28.6 28.4
V DD -O VP (V)
I D D-O P (A )
2.6 2.5 2.4 2.3 2.2 2.1 2.0 -40 -25 -10 5 20 35 50 65 80 95 110 12 5
28.2 28.0 27.8 27.6 27.4 27.2 27.0 -40 -25 -10 5 20 35 50 65 80 95 11 0 125
Figure 5.
74 72 70 68 66 64 62 60
-4 0 -2 5 -1 0 5
IDD-OP vs. Temperature
7 .6 5 7 .6 0 7 .5 5
Figure 6. VDD-OVP vs. Temperature
V VR EF (V )
(k H z )
7 .5 0 7 .4 5 7 .4 0 7 .3 5
f
O SC
20
35
50
65
80
95
110
125
-4 0
-2 5
-1 0
5
20
35
50
65
80
95
110
125
Figure 7.
1 .10
fOSC vs. Temperature
1 .9 5
Figure 8. VVREF vs. Temperature
1 .08
1 .9 3
1 .06
V RM S-U VH (V )
-4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 125
V RM S-UVL (V )
1 .9 1
1 .04
1 .8 9
1 .02
1 .8 7
1 .00
1 .8 5 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 110 12 5
Figure 9. VRMS-UVL vs. Temperature
2 .5 0 50 0 45 0 2 .4 5 40 0 35 0
Figure 10. VRMS-UVH vs. Temperature
V F B PF C-R D (V )
I R DY-LEK (n A )
-4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 125
30 0 25 0 20 0 15 0 10 0 50
2 .4 0
2 .3 5
2 .3 0
0 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 125
Figure 11.
VFBPFC-RD vs. Temperature
Figure 12. IRDY-LEK vs. Temperature
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1
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FAN6982 -- CCM Power Factor Correction Controller
Typical Performance Characteristics (Continued)
2 .6 0 2 .5 8 2 .5 6 2 .5 4 90 85 80
G m V (m h o )
V REF (V )
2 .5 2 2 .5 0 2 .4 8 2 .4 6 2 .4 4 2 .4 2 2 .4 0 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 125
75 70 65 60 55 50 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 125
Figure 13.
10 8 6 4
VREF vs. Temperature
120 110
Figure 14.
GmV vs. Temperature
V O F FSET (m V )
2 0 -2 -4 -6 -8 -1 0 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 12 5
G m I (m h o )
100 90 80 70 60 50 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 12 5
Figure 15.
2 .8 0 2 .7 9 2 .7 8
VOFFSET vs. Temperature
2 2 .0 2 1 .5 2 1 .0 2 0 .5
Figure 16. GmI vs. Temperature
V F BPF C -O VP (V )
2 .7 7
I T C (A )
2 .7 6 2 .7 5 2 .7 4 2 .7 3 2 .7 2 2 .7 1 2 .7 0 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 125
2 0 .0 1 9 .5 1 9 .0 1 8 .5 1 8 .0 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 125
Figure 17. VFBPFC-OVP vs. Temperature
-1 .0 5 0 .8 7 0 .8 5 -1 .0 7 -1 .0 9 -1 .11
Figure 18.
ITC vs. Temperature
V PF C-ILIM IT (V )
0 .8 3
V O(G M ) (V )
0 .8 1 0 .7 9 0 .7 7 0 .7 5 0 .7 3 0 .7 1 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 125
-1 .1 3 -1 .1 5 -1 .1 7 -1 .1 9 -1 .2 1 -1 .2 3 -1 .2 5 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 125
Figure 19. VO(GM) vs. Temperature
Figure 20. VPFC-ILIMIT vs. Temperature
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1
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FAN6982 -- CCM Power Factor Correction Controller
Typical Performance Characteristics (Continued)
17 17 16
0 .6 0
0 .5 5
V GAT E-CLAM P (V )
V PF C -UVP (V )
16 15 15 14 14 13 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 125
0 .5 0
0 .4 5
0 .4 0 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 125
Figure 21. VGATE-CLAMP vs. Temperature
Figure 22.
VPFC-UVP vs. Temperature
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1
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FAN6982 -- CCM Power Factor Correction Controller
Functional Description
Oscillator
The internal oscillator frequency of FAN6982 is determined by the timing resistor and capacitor on the RT/CT pin. The frequency of the internal oscillator is given by: (1 ) The dead time for the PFC gate drive signal is determined by (2 ) The dead time should be smaller than 2% of switching period to minimize line current distortion around line zero crossing.
G 1 VRMS 2
f OSC =
1 0.56 RT CT + 360CT
t DEAD = 360CT
VRMS VRMS-UVP
Figure 24. Modulation Gain Characteristics
VIN
Gain Modulator
Gain modulator is the key block for PFC stage because it provides the reference to the current control error amplifier for the input current shaping, as shown in Figure 23. The output current of gain modulator is a function of VEA, IAC and VRMS. The gain of the gain modulator is given as a ratio between IMO and IAC with a given VRMS when VEA is saturated to high. The gain is 2 inversely proportional to VRMS , as shown in Figure 24, to implement line feed-forward. This automatically adjusts the reference of current control error amplifier according to the line voltage such that the input power of PFC converter is not changed with line voltage, as shown in, Figure 25.
VEA
IL
Figure 25. Line Feed-Forward Operation To sense the RMS value of the line voltage, an averaging circuit with two poles is typically employed as shown in Figure 23. Notice that the input voltage of PFC is clamped at the peak of the line voltage once PFC stops switching since the junction capacitance of bridge diode is not discharged, as shown in Figure 26. Therefore, the voltage divider for VRMS should be designed considering the brownout protection trip point and minimum operation line voltage.
IMO = G I AC = I AC K (VEA - 0.6) VRMS 2 (VEAMAX - 0.6)
PFC runs VIN
PFC stops
Figure 23. Gain Modulator Block
VRMS
Figure 26. VRMS According to the PFC Operation
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1 www.fairchildsemi.com 12
FAN6982 -- CCM Power Factor Correction Controller
The rectified sinusoidal signal is obtained by the current flowing into the IAC pin. The resistor RIAC should be large enough to prevent saturation of the gain modulator as:
The current-control feedback loop also has a pulse-bypulse current limit comparator that forces the PFC switch to turn off if the ISENSE pin voltage drops below -1.15V until the next switching cycle.
2VLINE . BO MAX G < 159 A RIAC
(3)
Voltage-Control of Boost Stage
The voltage-control loop regulates PFC output voltage using internal error amplifier such that the FBPFC voltage is same as internal reference of 2.5V. To improve system efficiency at low AC line voltage and light-load condition, FAN6982 provides adjustable PFC output voltage. As shown in Figure 29, FAN6982 monitors VEA and VRMS to adjust the PFC output voltage. When VEA and VRMS are lower than thresholds, internal current source of 20A is enabled that flows through RFB2, increasing the voltage of the FBPFC pin. This causes the PFC output voltage to reduce when 20A is enabled as:
where VLINE.BO is the line voltage that trips brownout MAX protection, G is the maximum modulator gain when VRMS is 1.08V, and 159A is the maximum output current of the gain modulator.
Current-Control of Boost Stage
As shown in Figure 27 the FAN6982 employs two control loops for power factor correction, a currentcontrol loop and a voltage-control loop. The currentcontrol loop shapes inductor current, as shown in Figure 28, based on the reference signal obtained at IAC pin as:
I L RCS 1 = I MO RM = I AC G RM
(4)
VOPFC 2 =
RFB1 + RFB 2 x (2.5 - 20 A x RFB 2 ) RFB 2
(5)
Figure 29. Block of Adjustable PFC Output
Brownout Protection
FAN6982 has a built-in internal brownout protection comparator monitoring the voltage of the VRMS pin. Once the VRMS pin voltage is lower than 1.05V, the PFC stage is shutdown to protect the system from over current. FAN6982 starts up the boost stage once the VRMS voltage increases above 1.9V. Figure 27. Gain Modulation Block
IAC
TriFault DetectTM
To improve power supply reliability, reduce system component count, and simplify compliance to UL 1950 safety standards; the FAN6982 includes TriFault Detect technology. This feature monitors FBPFC for certain PFC fault conditions. In the case of a feedback path failure, the output of the PFC could exceed operating limits. Should FBPFC go too low, or too high, or open; TriFault Detect senses the error and terminates the PFC output drive. TriFault detect is an entirely internal circuit. It requires no external components to serve its protective function.
I MO
RM RCS1
IL
Figure 28. Inductor Current Shaping
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FAN6982 -- CCM Power Factor Correction Controller
PFC Soft-Start Function
The FAN6982 PFC soft-start function is shown in Figure 30. When bulk voltage is under the 96% of setting voltage; VEA clamps to 2.8V, the output current of multiplier cuts half, the rectifier line current is limited by current loop, and PFC output rise time increases. When bulk voltage is over 96%, the clamping function is disabled, and the bulk voltage can be regulated by voltage error amplifier. There have two advantages with PFC soft-start: one is the MOSFET experience of current is reduced, which can obtain more de-rating with MOSFET current level. The other one is to reduce the overshoot of PFC bulk voltage at the rising time because the charge current becomes small, the bulk voltage can not exceed to setting voltage easily.
RDY Function
The FAN6982 RDY function, is shown in Figure 31, is controlled by voltage of FBPFC. If the voltage of FBPFC is over than 96% of 2.5V, the RDY pin is connected to SGND. If the FBPFC is under the 46% of 2.5V, the RDY appears open-drain situation. Usually the capacitor is parallel with the RDY pin to prevent the layout noise. The PNP transistor can control the AHB LLC or dualforward controller on the same side or the "op-to" to control the LLC controller on the other side.
Figure 31. RDY Application Circuit
Figure 30. PFC Soft-Start
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FAN6982 -- CCM Power Factor Correction Controller
Physical Dimensions
Figure 32. 14-Pin Small Outline Package (SOIC)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.1
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FAN6982 -- CCM Power Factor Correction Controller
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